Method of reworking structures incorporating low-k dielectric materials

ABSTRACT

Methods of etching a semiconductor structure using ion milling with a variable-position endpoint detector to unlayer multiple interconnect layers, including low-k dielectric films. The ion milling process is controlled for each material type to maintain a planar surface with minimal damage to the exposed materials. In so doing, an ion beam mills a first layer and detects an endpoint thereof using an optical detector positioned within the ion beam adjacent the first layer to expose a second layer of low-k dielectric film. Once the low-k dielectric film is exposed, a portion of the low-k dielectric film may be removed to provide spaces therein, which are backfilled with a material and polished to remove the backfill material and a layer of the multiple interconnect metal layers. Still further, the exposed low-k dielectric film may then be removed, and the exposed metal vias polished.

FIELD OF THE INVENTION

The present invention relates to methods and systems for unlayeringmulti-layer structures incorporating low-k dielectric materials.

BACKGROUND OF THE INVENTION

Advanced semiconductor designs typically incorporate planarizedmultilevel structures including alternating layers of insulatingmaterials supporting dual damascene and single damascene metalinterconnections. Exemplary structures include alternating layers ofinsulating films, for example low-k dielectric films, with alternatingchemical-mechanical hardmask endstop layers, for example silicon nitrideand/or high density plasma oxide. Damascene metal can comprise, forexample, copper.

Selective unlayering of these multilayer structures is often necessaryfor purposes of manufacturing rework or recovery of wafers, to performdefect yield analysis, and/or for electrical characterization orphysical failure analysis of wafers, wafer fragments, individual dies,or packaged dies to perform reliability defect root cause analysis.Regular unlayering of these multi-layer structures can also be done inthe course of automated pattern recognition inspection of defects incomparison with electrical test maps.

Unlayering multi-layer structures including low-k dielectric materialsis problematic using known layer removal techniques. In particular, thefragile nature of the low-k dielectric materials cause them to reactpoorly to processes effective for oxides. For example, the lower modulusof low-k dielectric films are susceptible to damage when exposed toconventional chemical-mechanical polish processes. Wafer delayering formanufacturing rework or recovery of wafers cannot employ conventionaldelayering processes using plasma, or reactive ion etching orchemical-mechanical polish removal for planar deprocessing low-k filmswithout damaging underlying films and undercutting metal layers. Stillother techniques involving incident gallium ion beams can result inundesirable implantation of gallium into the low-k films or produce beaminteractions (i.e. chemical bond breakdown in organic components presentin some low-k films) producing unwanted electrical leakage paths andelectrical shorts.

Further, conventional processes used to remove overlying metal layers,particularly copper single damascene and copper dual damascene metal,can result in damage to the underlying low-k dielectric layers. Forexample, conventional chemical-mechanical removal of copper layers caneasily scratch, or embed polishing media or slurry into, underlyinglow-k films, by compromising hardmask endstop materials. Attempts tounlayer multilevel structures using conventional reactive ion etchingcan produce non-planar etch results due to the presence of porousregions within the low-k film as well as the in-homogenity of the low-kfilms, themselves.

Conventional reactive ion etching of copper requires elevatedtemperatures, producing nonvolatile species that can contaminate low-kdielectric films. Further, reactive ion etch removal of overlyinginsulating films can result in undercutting of underlying copper metallayers resulting in non-uniform etch removal of underlying low-kdielectric films.

New and improved processes are thus desirable which facilitate theselective planar de-processing of metal layers, hardmask materials andchemical-mechanical endstop materials over low-k dielectric filmswithout damaging the underlying low-k dielectric layers.

SUMMARY OF THE INVENTION

Two proposed methods involving deprocessing low-k structures with coppermetallurgy/copper interconnections are described.

First, a new and improved apparatus and methods involving collimatedArgon ion beam milling/Chemical assisted Argon Ion beam etching isprovided for unlayering multi-layer structures including low-kdielectric layers with mininal damage to the low-k dielectric filmswhile maintaining planarity of the unlayered surface. Such methods andapparatus are applicable, for example, to unlayering back-end multilevelmetallurgy found in semiconductor devices.

In accordance with one embodiment of the invention, there is provided amethod of ion beam etching a semiconductor structure including a firstlayer of material overlaying a second layer of low-k dielectric film,comprising the steps of: ion beam-milling the first layer of material;and detecting, with an optical detector positioned in the ion beamadjacent the first layer of material, an endpoint of the first layer;whereby to expose the second layer of low-k dielectric film.

In another embodiment of the invention, there is provided a system fordelayering a semiconductor structure including a first layer of materialoverlaying a second layer of low-k dielectric film, comprising: aprocessing chamber; an ion beam milling source in the processing chamberfor generating a beam of ions to mill the semiconductor structure; aplaten in the processing chamber for supporting the semiconductorstructure in the beam of ions; a sapphire crystal endpoint detector inthe processing chamber; a photospectrometer outside of the processingchamber; means for connecting the sapphire crystal endpoint detector tothe photospectrometer; and means for positioning the sapphire crystalendpoint detector proximate the platen to monitor milling of thesemiconductor structure.

Secondly, a set of processes for deprocessing spun-on low-k structureswith copper metallurgy/copper interconnections is described.

DESCRIPTION OF THE DRAWING FIGURES

These and other objects, features and advantages of the invention willbe apparent from a consideration of the Detailed Description of theInvention when read with consideration of the drawing Figures, in which:

FIG. 1 is a cross-sectional view of a semiconductor device including aback-end, multilevel metal contact structure exemplary of one type towhich the invention is applicable; and

FIGS. 2-7 are cross-sectional views of the multilevel metal contactstructure of FIG. 1 showing successive processing steps in accordancewith one embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Methodology for Reworking/Recovering Whole Wafers/WaferFragments/Individual Die:

With reference now to FIG. 1, there is shown a semiconductor structure16 including a silicon device front-end 20 overlain by a multilevelmetal back-end structure 18. Front end 20 comprises a conventionalsilicon-on-insulator (SOI) construction including a device-bearing,doped semiconductor layer 26 overlying an insulator layer 24 over asingle-crystal silicon layer 22. Semiconductor devices formed byimplantation and processing in layer 26 are contacted through back-endstructure 18 in the manner described below.

Continuing with reference to FIG. 1, back-end structure 18 is seen tocomprise a first-level connector layer including an insulator layer 28A,such as an oxide, having a metal-filled via 28B for contactingsemiconductor devices on doped silicon layer 26. Metal-filled via 28Bcontacts a source/drain region on the surface of doped silicon layer 26adjoining a gate structure 28C of a semiconductor field-effecttransistor (FET). If the gate material is silicon oxide, this device isfurther identified as a metal-oxide FET, or MOSFET.

A series of four layers of a low-k dielectric material, indicated at30A, 32A, 34A and 36A, respectively, overlay layer 28A, each low-k layerin turn overlain by an insulator layer 30B, 32B, 34B and 36B. Insulatorlayers 30B-36B each comprises a hardmask, chemical-mechanical endstop,such as a nitride, which will be used, in a manner described below, asan etching mask in a process for exposing the underlying low-kdielectric layer. Each series of low-k film/insulator layers 30A/B-36A/Bincludes a metal-filled via interconnect extending there through, themetal-filled vias indicated respectively at 30D, 32D, 34D and 36D. Aseries of metal connector layers, indicated respectively at 30C, 32C,34C and 36C, are interposed between adjacent vias.

Two oxide layers, indicated respectively at 38 and 40, overlie insulatorlayer 36, each oxide layer including a metal-filled via 38D, 40D andoverlying metal layer 38C, 40C. A respective silicon nitridechemical-mechanical etch stop layer, 38A, 40A, overlies each oxide layer38,40.

It will be appreciated that back-end structure 18 illustrates aconventional multilevel metal structure with a first interconnect 28B,for example comprising tungsten, overlaid by six, and optionally more,levels of metal vias and connectors graphically represented by 30C/D,32C/D, 34C/D, 36C/D, 38C/D and 40C/D. Typically, these metalinterconnections comprise dual damascene copper and single damascenecopper. In the described embodiment of the invention, the tungsten metalwiring level identified as 28B combined with the successive overlyingcopper metal lands identified as 30C, 32C, 34C, 36C, 38C and 40C wouldcomprise what is known in the art as ‘seven level metal.’ Variousmethods and materials are known in the art for fabricating this type ofstructure.

As described above, low-k dielectric layers are identified at 30A-36A.Typically, these low-k dielectric layers comprise materials having a kfactor of about 2.85 or less. Such films typically comprisePECVD-deposited SiCOH films and compounds thereof, PECVD-depositedcarbon-doped oxides and other organic polymers and porous oxides.Commercially available low-k dielectric products and materials includeDow Corning's SiLK™ and porous SiLK™, Applied Materials' Black Diamond™,Novellus' Coral™, Honeywell's HOSP™, and Trikon Technologies FLOWFILL™,among others.

Low-k dielectric films have desirable electrical characteristicseffective to significantly reduce the lateral and inter-level capacitiveeffects between closely spaced electrical conductors of multilevelmetal. Such conductors include, for example, the dual damascene-formedcopper conductors described above.

As noted above, however, these low-k dielectric materials possesscertain chemical and mechanical characteristics that make them prone todamage from certain common semiconductor processes. They are, forexample, soft, pliable and porous as well as susceptible to damagethrough the use of typical semiconductor processes. Processes typicallyused to remove or unlayer low-k dielectric materials, such as mechanicalunlayering, reactive ion etching (RIE), focused ion beam (FIB)techniques, chemical-mechanical polishing and wet chemical removalprocesses may damage the low-k or cause conductive leakage paths withinthe dielectric layers themselves.

It will be understood that the terms “layer” and “film,” and variantsthereof, are used interchangeably herein to describe the thin, conformalsheets of semiconductor, insulator and conductive materials thatcomprise a semiconductor device structure. It will be further understoodthat the terms “low-k dielectric material” and “SiLK,” and variantsthereof, are used interchangeably herein to described the low-kdielectric materials described above.

With reference now to FIG. 2, there is shown semiconductor structure 16having hardstop layer 40A and oxide layer 40 removed down to via 40D.Partial oxide layer 40 may be removed using one of many known processesincluding, for example, chemical-mechanical polishing or reactive ionetching.

As further shown in FIG. 2, structure 16 is situated in a processingchamber 48, comprising, for example, one of many commercially knownvacuum chambers available with a vacuum feedthrough and a tungstenfilament ion beam source or a filament-less source. Processing chamber48 supports structure 16 on a liquid-cooled platen 46 capable of fullrotation and full tilt and of cooling in a range of −15 to +35 degreescentigrade.

In the described embodiment, a cooling media of 50% di-ionized water and50% ethylene glycol-antifreeze is used to control the temperature ofstructure 16, preventing damaging overheating from incident ion beamenergy by heat exchange cooling of platen 46. Structure 16 is attachedto platen 46, for example, using heat dissipating grease. Alternatively,a cooling helium gas can be metered into a fixture (not shown) holdingstructure 16 for incident ion beam delayering. Processing chamber 48accommodates a line 50 for introducing a focused input of a controlledmixture of a selected processing gas(es) 51 into the chamber. Processingchamber 48 further supports an argon ion beam milling source 52.

In the described embodiment, ion beam milling source 52 is manufacturedby milling tool manufacturer VEECO instruments. The system has beenmodified with the addition of a gas nozzle for introducing gases intothe chamber. Further included are four individual mass flow controllersfor metering separate gases controlled via an external computer (notshown) having a conventional RS232 interface to monitor gas flow rates.

In the described embodiment, milling source 52 comprises a 400 wattpulse-mode 30 kHz switchable DC power supply, avoiding the risk ofcharge-inducted damage that may be associated with conventional 13.56mHZ RF generators typically used in RIE/PLASMA etching systems. Millingsource 52 preferably includes a circumferential charge neutralizingfilament 53 surrounding the collimated Argon beam. Milling source 52 iscapable of currents in the range of 300 eV-3 KeV for a full range ofincident beam energies.

While the invention is described with respect to Argon ion beam milling,any inert noble gas species found in the same column of the periodictable as Argon, including helium, neon, xenon, and radon would work.Noble gases ionize in a plasma to form non reactive, inert ions. Argongas is typically selected for all plasma processes because it isinexpensive and requires the least energy to disassociate into ions andform a plasma.

Processing chamber 48 further includes a fiber optic photospectrometerendpoint detector system 54. Endpoint detector system 54 includes asapphire tip detector 56 positioned within the argon ion beam near theregion of interest on semiconductor structure 16. Sapphire tip detector56 is connected, through a ferro-fluidic vacuum feed-throughaccommodating a stainless steel tube housing an appropriate fiber opticcable, the tube and cable assembly indicated at 57, to apersonal-computer based charge-coupled device (CCD) CCD UV-VIS arrayspectrophotometer 58 located outside of chamber 48. In the describedembodiment, a standard PCI card is used for interfacingspectrophotometer 58 with a computer (PC) 60. The tube/cable 57 ispreferably motor operated in a conventional manner by anelectromechanical positioning device 59 so that detector 56 can berepositioned at various process steps to be proximate regions ofinterest on semiconductor substrate 16.

In a manner known in the art, spectrophotometer 58 can be tuned tovarious peak sensitivities, including copper peak sensitivity, tantalumliner peak sensitivity, carbon peak sensitivity (for such organic low-kdielectric films as SiLK), silicon peak sensitivity (for PECVD siliconoxide and LPCVD/HDP silicon nitride dielectrics), as well as tungstenpeak sensitivity for tungsten interconnection, to detect different typesof endpoint materials. This spectrophotometer may, for example, becontrolled using PC 60 running Visual C++ software code.

As is further described below, the above-described equipment is used inan argon ion beam milling process to etch back end structure 18,including the various insulator, metal and low-k dielectric film layers.It will be seen that the etching process results in highly controllable,essentially planar delayering, while avoiding the damage to low-kmaterials typically associated with prior art processes, including:damage caused by FIB gallium beam induced charge implantation,undesirable anisotropic etch profiles associated with reactive ionetching (RIE) etch profiles, oxygen and H2O uptake in SiLK low-k films,solvent uptake in low-k dielectric films as well as susceptibility toscratching/slurry particle embodiment damage by chemical-mechanicalprocessing.

Applicant has developed the following, exemplary operating parametersfor planarizing low-k dielectric films:

For planarizing Dow Corning Porous SiLK (porous methyl silsequioxane;k=2.2)

-   -   Argon ion beam currents in the range of 100 mA/cm² to 150 mA/cm²        (maximum of 300 mA/cm²)    -   Accelerating voltages in the range of 300 eV to 400 eV (maximum        of 650 eV)    -   Angle of Incidence of Argon Beam to stage/sample surface in the        range of 7 degrees up to 21 degrees (93 degrees from normal to        79 degrees from normal);    -   Chuck temperature control in the range of 0 degrees centigrade        to 15 degrees centigrade (maximum)    -   Heat transfer/heat conduction to liquid cooled chuck; Silicone        based grease such as MUX for minimum out-gassing and greatest        heat dissipation    -   Stage rotation: about 10 rpm    -   Charge Neutralizing Current: about 300 uA (maximum)    -   Argon Magnet Voltage Level: in the range of about 0.80 mV to        0.85 mVolts        These parameters will result in an etch rate in the range of 250        A/minute to 440 A/minute, depending on incident angle and beam        current.

For planarizing Dow Corning SiLK (k=2.65)

-   -   Beam Currents in the range of 150 mA/cm² to 250 mA/cm cm²    -   Accelerating voltages in the range of 400 eV to 500 eV (maximum        of 650 eV)    -   Angle of Incidence of Argon Beam to stage/sample surface in the        range of 7 degrees up to 21 degrees (93 degrees from normal to        79 degrees from normal);    -   Chuck temperature control in the range of 0 degrees centigrade        to 15 degrees centigrade (maximum)    -   Heat transfer/heat conduction to liquid cooled chuck; Silicone        based grease such as MUX for minimum out-gassing and greatest        heat dissipation    -   Stage rotation; about 10 rpm    -   Charge Neutralizing Current: about 300 uA (maximum)    -   Argon Magnet Voltage Level; in the range of about 0.80 to 0.85        mV        These parameters will result in an etch rate in the range of 225        A/minute to 400 A/minute, depending on incident angle and beam        current.

Still with reference to FIG. 2, assembly 57 is used to position sapphiredetector 56 proximate the upper surface of remaining oxide layer 38.Spectrophotometer 58 is adjusted to sense nitride, by optimizing thesignal to detect silicon nitride. A selected gas 51, for example amixture of CF4 and oxygen, is introduced into chamber 48 and theparameters of ion beam milling source 52 and platen 46 are adjusted in aconventional manner to optimize the etching of oxide and copper. Themixture of CF4 gas and oxygen will preferentially etch oxide and nitridewithout attacking copper. Ion beam milling would mill copper at one ratewhile ionized gas would preferentially etch oxide and nitride. Millingsource 52 is operated to remove the remaining portion of oxide layer 40along with the copper in copper-filled via 40. When photospectrometer 58detects nitride from nitride layer 38, the process is terminated.

With reference now to FIG. 3, photospectrometer 58 is adjusted to senseoxide by optimizing the signal to sense oxygen or silicon but NOTnitride, and the parameters of gas 51, milling source 52 and platen 46are optimized in a conventional manner to etch nitride and copper.Nitride layer 38A is thus removed along with copper conductor 38C,exposing the upper surface of remaining oxide layer 38 and copper filledvia 38D as shown in FIG. 3.

It will be understood that following each etching step, assembly 54 andplaten 46 are manipulated to place semiconductor structure 16 andendpoint detector 56 in the optimum physical position for the next etchstep. Endpoint detector 56 can be placed directly within the ion beam ofmilling source 52 proximate the areas of interest being etched. Thetemperature, angle and position of platen 46 are adjusted to optimizethe etch process for the materials being etched.

With reference now to FIG. 4, photospectrometer 58 is adjusted to sensea low-k dielectric film such as SiLK by optimizing for sensing a carbonpeak, the principal elemental component of an organic low-k film. Bysensing the appropriate principal elemental component, i.e. forconventional oxides, this would be oxygen or silicon; for siliconnitride, this would be nitrogen, the above-described etching processesare used to remove the remaining portion of oxide layer 38, nitridelayer 36 and the copper connectors and copper-filled vias there through,exposing low-k dielectric layer 36A and copper-filled via 36D as shownin FIG. 4.

It will be appreciated from a consideration of the process descriptionand drawings that the etching systems and processes that are the subjectof the present invention yield highly planar exposed surfaces,regardless of the materials being etched. Further, the processes can becontrolled to accurately etch very thin films and very small depthswithin films, thus enabling the exposure of substantially any desiredlayers or features within a semiconductor structure.

With reference now to FIGS. 5 and 6, structure 16 is shown with theabove-described process steps repeated to expose low-k dielectric layers34A (FIG. 5) and 32A (FIG. 6), respectively. The etching processes usedto remove the intermediate nitride layers and copper metallurgy aresubstantially identical to those described above. Endpoint detector 56and platen 46 are repositioned intermediate each etching step, in themanner described above, to optimize both the etching process and theendpoint detection.

With reference now to FIG. 7, semiconductor structure 16 is shown withall of back-end structure 18 removed excepting a remaining portion oflayer 30A overlying layer 28A, and the associated metallurgy 30D, 28Band FET gate 28C.

Methodology for Unlayering/Reworking Individual Die and Wafer Fragmentswith Low-K Dielectric Films Using Mechanical Polish/Removal ofMetal/Metal Interconnects Combined with RIE or Plasma DeprocessingSteps:

The following methods allow for unlayering/deprocessing of Low-K spun-ondielectric films where each low k dielectric level has been built (ie.Hardmask, CMP endstop layer is intact) before unlayering/deprocessing isinitiated.

Method (a)

Using a RIE etch (ie. CF4 process gas) or wet etch, remove nitride caplayer and hardmask (ie. Applied Materials BLOK™). Next remove spun-onLow-K Dielectric with Oxygen Plasma Next deposit an oxide ortetraothrosilicate (TEOS) CVD layer to permit mechanical polish removalof metal/metal interconnection through the underlying SiLK layer to thehardmask or cap nitride layer. Next, deposit replacement cap layer.Resume normal spun on low k Dielectric film deposition.

Method (b)

Using a RIE etch (ie. CF4 process gas) or wet etch, remove nitride capand hard mask (ie. Applied Materials BLOK™). Partially remove spun onlow-K Film to top level of metal interconnection. Deposit oxide or CVDtetraorthosilicate insulator film in gap formerly occupied by low kspun-on dielectric film. Mechanically polish/remove via level/metalinterconnection and metal level itself. Deposit CVD nitride cap layer.Resume normal spun-on low k dielectric film (ie. Dow Corning SiLK) filmdeposition.

Method (c)

Mechanically polish to remove the nitride cap and hardmask layeroverlying metal and low-K spun on dielectric film. Remove spun-on low Kdielectric film with oxygen plasma process. Deposit oxide layer or CVDtetraorthosilicate (TEOS) dielectric film in the gap formerly occupiedby spun-on Low-k dielectric film. Mechanically polish to remove metallevel along with deposited oxide/TEOS layer through underlying nitridecap and stop on hardmask. Deposit new CVD nitride cap layer. Resumenormal spun-on low k dielectric film (ie. Dow Corning SiLK) deposition.

Method (d)

Mechanically polish to remove nitride cap and hardmask layer overlyingmetal and low-K spun on dielectric film. Partially remove spun-on low Kdielectric film with oxygen plasma process to top of metalinterconnection level. Deposit oxide layer or CVD tetraorthosilicate(TEOS) dielectric film in gap formerly occupied by spun-on Low-kdielectric film. Mechanically polish/remove metal level lines along withdeposited oxide/TEOS layer. Deposit new CVD nitride cap layer. Resumenormal spun-on low k dielectric film (ie. Dow Corning SiLK) deposition.

Method (e)

Use RIE (ie. CF4 process gas) or wet etch to remove nitride cap andhardmask layer (ie. BLOK ™). Alternatively, mechanically polish toremove nitride cap layer and hardmask layer (ie. BLOK™). Immerse samplein copper wet etch bath in order to remove metal and metalinterconnection levels. Next, wet etch barrier liner (ie. Ta/TaN)material. Next, Plasma etch with oxygen process gas to remove low-k spunon dielectric film. Mechanically polish/remove residual metalinterconnection layer and stop at hardmask material. Deposit replacementnitride cap layer. Resume normal spun-on low k dielectric film (ie. DowCorning SiLK) deposition. Complete BEOL build cycle.

Method (f)

Use RIE (ie. CF4 process gas) or wet etch to remove nitride cap andhardmask layer (ie. BLOK ™). Alternatively, mechanical polish removal ofthe cap nitride and hardmask could be substituted, instead. First,expose wafer to a slow copper etchant to controllably remove the coppermetal wiring levels and copper interconnection without etching into theunderlying copper metal lands. Once the copper lands and copperinterconnection levels are etched away (using a timed etch process),employ a different chemical etchant to remove the barrier linermetallurgy (typically a tantalum/tantalum nitride material) withoutattacking the underlying copper metal wiring. Next, perform an oxygenplasma etch to remove the spun on low-k dielectric film (ie. Dow CorningSiLK film) which will selectively stop on the underlying silicon nitridecap layer. Mechanically polish off the cap nitride along with anyresidual copper metallurgy and tantalum/tantalum nitride liner material.Redeposit CVD nitride cap layer. Resume normal spun-on low k dielectricfilm (ie. Dow Corning SiLK) deposition. Complete BEOL build cycle.

There have thus been described systems and methods using ion beametching with endpoint detection for selectively etching multi-layerstructures on semiconductor devices. The systems and methods of thepresent invention enable highly selective and controllable planarremoval of different types of materials, including oxides, nitrides,metals and low-k dielectrics such as SiLK. They further permit suchremoval without damaging the soft, fragile, low-k dielectric materials.There have further been a set of processes for deprocessing spun-onlow-k structures with copper metallurgy/copper interconnections.

The present invention can be used to facilitate, for example, thereworking and/or evaluation of semiconductor devices, particularly thoseincorporating low-k dielectric films. The invention thus has applicationin the manufacture, rework and analysis of semiconductor devices.

1-6. (canceled)
 15. A system for delayering a semiconductor structureincluding a first layer of material overlaying a second layer of low-kdielectric film, comprising: a processing chamber; an ion beam millingsource in said processing chamber for generating a beam of ions to millsaid semiconductor structure; a platen in said processing chamber forsupporting said semiconductor structure in said beam of ions; a crystalendpoint detector in said processing chamber; a photospectrometeroutside of said processing chamber; means for connecting said crystalendpoint detector to said photospectrometer; and means for positioningsaid crystal endpoint detector proximate said platen to monitor millingof said semiconductor structure.
 16. A system in accordance with claim15 wherein said crystal endpoint detector comprises a sapphire crystal.17. A system in accordance with claim 15 and further including means forintroducing a gas into said processing chamber.
 18. A system inaccordance with claim 15 wherein said ion beam milling source comprisesan Argon ion beam-milling source.
 19. A system in accordance with claim18 and further comprising a charge-neutralizing filament positioned toenclose the Argon ion beam when said Argon ion beam milling source is inoperation.
 20. A system in accordance with claim 15 wherein and furtherincluding means for cooling said semiconductor structure. 21-27.(canceled)
 28. A system in accordance with claim 15 wherein said platencomprises a liquid-cooled platen.
 29. A system in accordance with claim28 wherein said liquid-cooled platen is capable of cooling in a range of−15 to +35 degrees centigrade.
 30. A system in accordance with claim 15wherein said ion beam milling source comprises an inert noble gas.
 31. Asystem in accordance with claim 15 wherein said inert noble gas isselected from the group consisting of helium, neon, xenon, and radon.32. A system in accordance with claim 15 further including acircumferential charge neutralizing filament surrounding said ion beammilling source.
 33. A system in accordance with claim 15 wherein saidcrystal endpoint detector is positioned within said beam of ions formilling said semiconductor structure.
 34. A system for delayering asemiconductor structure including a first layer of material overlaying asecond layer of low-k dielectric film, comprising: a processing chamber;an ion beam milling source in said processing chamber for generating abeam of ions to mill said semiconductor structure; a platen in saidprocessing chamber for supporting said semiconductor structure in saidbeam of ions; and a fiber optic photospectrometer endpoint detectorsystem of said processing chamber having a crystal endpoint detectorresiding within said beam of ions for milling said semiconductorstructure.
 35. A system for delayering a semiconductor structureincluding a first layer of material overlaying a second layer of low-kdielectric film, comprising: a processing chamber; an ion beam millingsource in said processing chamber for generating a beam of ions to millsaid semiconductor structure; a platen in said processing chamber forsupporting said semiconductor structure in said beam of ions; a sapphirecrystal endpoint detector in said processing chamber; aphotospectrometer outside of said processing chamber; means forconnecting said sapphire crystal endpoint detector to saidphotospectrometer; and means for positioning said sapphire crystalendpoint detector proximate said platen to monitor milling of saidsemiconductor structure, wherein said sapphire crystal endpoint detectorresides within said beam of ions for milling said semiconductorstructure.
 36. A system in accordance with claim 35 wherein said ionbeam milling source comprises an inert noble gas selected from the groupconsisting of argon, helium, neon, xenon, and radon.
 37. A system inaccordance with claim 35 further including a circumferential chargeneutralizing filament surrounding said ion beam milling source.
 38. Asystem in accordance with claim 35 wherein said means for connectingsaid sapphire crystal endpoint detector to said photospectrometercomprises a fiber optic cable.
 39. A system in accordance with claim 38wherein said fiber optic cable is connected at a first end to saidsapphire crystal endpoint detector within said processing chamber and ata second end to said photospectrometer outside of said processingchamber.
 40. A system in accordance with claim 38 further including aferro-fluidic vacuum feed-through accommodating a stainless steel tubehousing said fiber optic cable.
 41. A system in accordance with claim 40wherein said stainless steel tube housing said fiber optic cable aremotor operated, said method further including an electromechanicalpositioning device for positioning said sapphire crystal endpointdetector to regions of interest on semiconductor substrate.